Algorithm/Architecture Co-Design of a Picture-Rate Up-conversion Module

نویسندگان

  • Aleksandar Beric
  • Gerard de Haan
چکیده

The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this paper, we analyse architectures that enable the design of a low-power picture-rate up-conversion module, which will be part of a System-on-Chip (SoC) for video format conversion. In order to cope with the huge memory, bandwidth and computational requirements of the application, numerous joint optimizations of algorithm and architecture are performed. Further, we use data compression to reduce the memory requirements and power dissipation. Finally, we use multi-level caching to exploit locality of reference, thereby reducing the data bus bandwidth requirements and power dissipation. Keywords— Up-converter, low-power, single-chip, data compression, motion estimation, motion compensation.

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تاریخ انتشار 2002